CMOS Amplifier Design with 30dB DC Gain
Project #1 of EE479L (Analog and Non-Linear Integrated Circuit Design) – Advisor: Prof. Dina El-Damak, University of Southern California This project is to design the amplifier with DC gain as 30dB. In this situation, the common source configuration is applied. Here is the lab report:
500 MHz Digital Phase Locked-Loop (DPLL)
Final Project of EE477L (MOS VLSI Circuit Design) – Advisor: Prof. Ali E. Zadeh, University of Southern California This project is to design and optimize a digital phase lock loop. The whole project consisted of two parts: DPLL Individual Blocks: Design both schematics and layout of each block including Phase Frequency Detector, Charge Pump, Voltage Control…
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