500 MHz Digital Phase Locked-Loop (DPLL)
Final Project of EE477L (MOS VLSI Circuit Design) – Advisor: Prof. Ali E. Zadeh, University of Southern California
This project is to design and optimize a digital phase lock loop. The whole project consisted of two parts:
- DPLL Individual Blocks: Design both schematics and layout of each block including Phase Frequency Detector, Charge Pump, Voltage Control Oscillator, Divide-by-10 Circuit.
- Build the complete circuit and optimized the performance in clock cycle, power consumption and area.
Here is the report:
EE477_Project3_Report